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Cadence Collaborates with GUC on AI, HPC and Networking in Advanced Packaging Technologies

Cadence Collaborates with GUC on AI, HPC and Networking in Advanced Packaging Technologies
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Igor elkanovichGlink cowoSanjive agarwalaDan kochpatcharinCadence design systems incGlobal unichip corpIp group at cadenceDesign infrastructure management divisionCadence design systemsGlobal unichipIntelligent system designIntelligent system design strategy

Cadence Collaborates with GUC on AI, HPC and Networking in Advanced Packaging Technologies

Cadence Collaborates with GUC on AI, HPC and Networking in Advanced Packaging Technologies
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Sanjive agarwalaGlink cowoDan kochpatcharinIgor elkanovichGlobal unichip corpIp group at cadenceCadence design systems incCompanies to workDesign infrastructure management divisionDesign systemsGlobal unichipIntelligent system designIntelligent system design strategyCadence design systems

CADENCE DESIGN SYSTEMS, INC : Stock Market News and Information | CDNS| US1273871087

Cadence 112G-LR SerDes silicon proven in GUC’s HBM3/GLink/CoWoS platform . | April 26, 2023

Igor elkanovichGlink cowoDan kochpatcharinSanjive agarwalaIp group at cadenceDesign infrastructure management divisionCadence design systems incCompanies to workGlobal unichip corpCadence design systemsGlobal unichipIntelligent system designIntelligent system design strategyIntelligent systemNc stock exchangePress release

Cadence Tapes Out 16G UCIe Advanced Package IP on TSMC s N3E Process Technology – EEJournal

SAN JOSE, Calif., April 24, 2023 Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the tapeout of Cadence® 16G UCIe™ 2.5D advanced package IP on TSMC’s 3nm (N3E) process technology. Implemented on TSMC’s 3DFabric™ CoWoS-S silicon interposer technology, the IP offers ultra-high bandwidth density, efficient low-power performance and superior low latency, making it ideal for…

Debendra das sharmaSanjive agarwalaCadence design systems incIp group at cadenceUcie consortiumCadence design systemsCadence verificationAdvanced packageIntelligent system design

Cadence Accelerates Hyperscale SoC Design with Next-Generation 112G Extended Long-Reach SerDes IP on TSMC s N4P Process – EEJournal

Highlights: • DSP-based, flexible-rate SerDes IP is optimized for PPA for next-generation cloud networking, AI/ML, and 5G wireless applications • New architecture delivers exceptional ELR performance and enables system robustness for lossy and reflective channels • The IP supports ELR, LR, MR and VSR applications and provides a flexible power-saving capability over different channels SAN…

Dan kochpatcharinSanjive agarwalaDesign infrastructure management divisionCadence design systems incIp group at cadenceCadence design systemsExtended long reachMedium reachVery short reachCadence intelligent system design