Cadence Accelerates Hyperscale SoC Design with Next-Generation 112G Extended Long-Reach SerDes IP on TSMC's N4P Process – EEJournal

Highlights: • DSP-based, flexible-rate SerDes IP is optimized for PPA for next-generation cloud networking, AI/ML, and 5G wireless applications • New architecture delivers exceptional ELR performance and enables system robustness for lossy and reflective channels • The IP supports ELR, LR, MR and VSR applications and provides a flexible power-saving capability over different channels SAN…

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Dan Kochpatcharin ,Sanjive Agarwala ,Asics ,Design Infrastructure Management Division ,Nasdaq ,Cadence Design Systems Inc ,Ip Group At Cadence ,Cadence Design Systems ,Extended Long Reach ,Medium Reach ,Very Short Reach ,Cadence Intelligent System Design ,