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Cadence Accelerates Intelligent SoC Development with Comprehensive On-Device Tensilica AI Platform – Consumer Electronics Net
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Cadence Accelerates Intelligent SoC Development with Comprehensive On-Device Tensilica AI Platform
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Cadence Announces New Low-Power IP for PCI Express 5.0 Specification on TSMC N5 Process
Cadence Design Systems, Inc. announced immediate availability of Cadence® IP supporting the PCI Express® (PCIe®) 5.0 specification on TSMC N5 process technology. The next follow-on version on TSMC N3 process technology is expected to be taped out in early 2022. Collaboration with major customers is ongoing for N5 SoC designs targeting hyperscale computing and networking applications. The Cadence IP for PCIe 5.0 technology consists of a PHY, companion controller and Verification IP (VIP) targeted at SoC designs for very high-bandwidth hyperscale computing, networking and storage applications. With Cadence’s PHY and Controller Subsystem for PCIe 5.0 architecture, customers can design extremely power-efficient SoCs with accelerated time to market.
Third-generation 112G-LR SerDes IP Cadence Design Systems has unveiled its third-generation 112G long-reach (112G-LR) SerDes IP on TSMCâs N5 process, targeting hyperscale ASICs, AI/ML accelerators, and switch fabric systems on chip (SoCs).
The new architecture offers 25% power savings, 40% area reduction and better design margins over the second-generation architecture, and looks to address the increasing needs for higher performance and power efficiency in modern next-generation cloud data centres.
Cadence has enabled different variances of PAM4 SerDes supporting XSR, VSR, MR and LR interconnect standards and through a combination of design wins and collaborations with leading hyperscale and data centre customers, has been able to incorporate specific enhancements in the third-generation product and currently has N5 test chips in-house that are undergoing characterization.
Cadence unveils low-power IP for PCI Express 5.0 specification on TSMC N5 process Cadence Design Systems is making available IP supporting the PCI Express (PCIe) 5.0 specification on TSMC N5 process technology, expected to be taped out in early 2022
The IP consists of a PHY, companion controller and Verification IP (VIP) targeted at SoC designs for very high-bandwidth hyperscale computing, networking and storage applications helping customers to design extremely power-efficient SoCs with accelerated time to market.
The Cadence IP offers a highly power-efficient implementation of the standard, with several evaluations from leading customers indicating it provides industry best-in-class power at the maximum data transfer rate of 32GT/s and worst-case insertion loss.
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