Cadence unveils low-power IP for PCI Express 5.0 specification on TSMC N5 process
Cadence Design Systems is making available IP supporting the PCI Express (PCIe) 5.0 specification on TSMC N5 process technology, expected to be taped out in early 2022
The IP consists of a PHY, companion controller and Verification IP (VIP) targeted at SoC designs for very high-bandwidth hyperscale computing, networking and storage applications helping customers to design extremely power-efficient SoCs with accelerated time to market.
The Cadence IP offers a highly power-efficient implementation of the standard, with several evaluations from leading customers indicating it provides industry best-in-class power at the maximum data transfer rate of 32GT/s and worst-case insertion loss.