Cadence unveils low-power IP for PCI Express 5.0 specification on TSMC N5 process Cadence Design Systems is making available IP supporting the PCI Express (PCIe) 5.0 specification on TSMC N5 process technology, expected to be taped out in early 2022
The IP consists of a PHY, companion controller and Verification IP (VIP) targeted at SoC designs for very high-bandwidth hyperscale computing, networking and storage applications helping customers to design extremely power-efficient SoCs with accelerated time to market.
The Cadence IP offers a highly power-efficient implementation of the standard, with several evaluations from leading customers indicating it provides industry best-in-class power at the maximum data transfer rate of 32GT/s and worst-case insertion loss.
PCI Express 4.0/3.0/2.1/1.1 Support The Northwest Logic Expresso 4.0 Core is part of Rambus’ PCI Express Solution. This solution is designed to achieve maximum PCI Express throughput while being easy to use.
The Expresso 4.0 Core separately, or in combination with Northwest Logic family of DMA Cores and DMA Drivers, provide the maximum system throughput on a PCI Express link. Contact Rambus for more details.
The core is specifically designed for ease of use including full receive packet decoding, complete error handling, automatic handling of PCI Express message packets and comprehensive system-debug and link monitoring support.
The core is delivered fully integrated and verified with the user’s Target PHY. Contact Rambus for a complete list of supported PHYs. To accelerate simulations, the core is also delivered integrated with a fast-simulating behavioral PHY.
PCI EXPRESS 5.0 transceiver and reference clock solution Tektronix, in collaboration with Anritsu, has introduced a PCI EXPRESS 5.0 transceiver (Base and CEM) and reference clock solution.
It is the first company to offer early CEM fixtures for pre-compliance testing. The collaboration between Tektronix and Anritsu enables receiver verification, complementing a leading transmitter and reference clock test suite.
PCI EXPRESS is viewed as the dominant high-speed serial computer bus and has been doubling bandwidth every three years and is exceeding that target with this aggressive introduction of the 5.0 Base Specification (128 GB/s).
This rapid pace of development is expected to continue as PCI-SIG, the standard-setting body for peripheral component I/O data transfers, has announced the PCI EXPRESS 6.0 specification (256 GB/s) which is to be delivered in 2021 and includes multi-level PAM4 signaling.