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Empowering AI-Enabled Systems with MIPI C/D-PHY Combo IP: The Complete Audio-Visual Subsystem and AI

In the realm of System-on-Chip (SoC) design, the integration of advanced camera and display capabilities is crucial for enabling Artificial Intelligence . ....

Farasan , Xinjiang , China , Artificial-intelligence , Camera-serial-interface , Display-serial-interface , Serial-interface , Improved-inter-integrated-circuit , Physical-layer , Wire-controller , Arasan-chip-systems

USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm

The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use . ....

Farasan , Xinjiang , China , Macrocell-interface-plus , Full-speed , Low-speed , Non-return-to-zero-inverted , Electro-static-discharge , Usb-phy , Sb-2-0-otg , Usb-otg

CAN-SEC Acceleration Engine IP Core

Arasan’s CAN-SEC Acceleration Engine Core implements the CAN-XL Protocol (CiA 610-1), CAN-XL Addon Part 1-Simple/Extercontent Indication (CiA 613-1), . ....

Farasan , Xinjiang , China , Engine-core , Extercontent-indication , Can-sec , An , Acceleration-engine , An-sec-acceleration-engine , Rasan-can-sec , P-core

USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm

The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use . ....

Farasan , Xinjiang , China , Macrocell-interface-plus , Full-speed , Low-speed , Non-return-to-zero-inverted , Electro-static-discharge , Usb-phy , Sb-2-0-otg , Usb-otg

xSPI - PSRAM Master IP Core

Arasan Chip System’s xSPI/PSRAM master IP is easy to use, simple to work with, quick to operate, and reliable under all conditions. It supports the . ....

Farasan , Xinjiang , China , Arasan-chip-system , Xspi- , Ospi , Spi-psram-master , Ureboot-xspi-psram-master , P-core , Ilicon-ip , Emiconductor-ip