Phase-change memory (PCM) has been considered a promising candidate for solving von Neumann bottlenecks owing to its low latency, non-volatile memory property and high integration density1,2. However, PCMs usually require a large current for the reset process by melting the phase-change material into an amorphous phase, which deteriorates the energy efficiency2–5. Various studies have been conducted to reduce the operation current by minimizing the device dimensions, but this increases the fabrication cost while the reduction of the reset current is limited6,7. Here we show a device for reducing the reset current of a PCM by forming a phase-changeable SiTex nano-filament. Without sacrificing the fabrication cost, the developed nano-filament PCM achieves an ultra-low reset current (approximately 10 μA), which is about one to two orders of magnitude smaller than that of highly scaled conventional PCMs. The device maintains favourable memory characteristics such
The metal–oxide–semiconductor field-effect transistor (MOSFET), a core element of complementary metal–oxide–semiconductor (CMOS) technology, represents one of the most momentous inventions since the industrial revolution. Driven by the requirements for higher speed, energy efficiency and integration density of integrated-circuit products, in the past six decades the physical gate length of MOSFETs has been scaled to sub-20 nanometres. However, the downscaling of transistors while keeping the power consumption low is increasingly challenging, even for the state-of-the-art fin field-effect transistors. Here we present a comprehensive assessment of the existing and future CMOS technologies, and discuss the challenges and opportunities for the design of FETs with sub-10-nanometre gate length based on a hierarchical framework established for FET scaling. We focus our evaluation on identifying the most promising sub-10-nanometre-gate-length MOSFETs based on the