Synopsys Extends Verification Hardware Market Leadership with Breakthrough Emulation Performance
Delivers Next-Generation Solution Enabling 10 MHz Performance, Power-Aware Emulation, and System-Level Debug
News provided by
Share this article
The industry s first SoC power-aware emulation system – ZeBu Empower
Debug optimized for multi-billion gate designs and billions of software cycles – ZeBu System Level Debug
70-100x emulation throughput gain with Virtualizer – ZeBu Hybrid Emulation
Rapid software development for PCI Express (PCIe) 5.0, USB3, SATA, Ethernet, and NVMe-based design – ZeBu Virtual Host and Device models
SNPS) today announced disruptive innovations in emulation delivering 10 MHz performance to speed hardware and software verification of complex system-on-chips (SoCs) in areas such as high-performance computing (HPC), 5G, GPU, artificial intelligence (AI) and automotive. The new ZeBu
Synopsys ZeBu Server 4 Adopted by Xsight Labs for Intelligent Networking Switch Processor
ZeBu s 7 Billion Gate Cloud Capacity Enabled Full Chip Debug for Complex Networking SoC Validation
News provided by
Share this article
® Server 4 emulation solution for validation of its X1 intelligent networking switch processor. ZeBu Server 4 s performance and 7 billion gate cloud capacity has enabled Xsight Labs to further strengthen its pre-tapeout validation methodology using complex networking workloads with full system-on-chip (SoC) emulation. ZeBu s performance has also enabled full system software driver development and maximum utilization of all X1 s Ethernet ports for networking performance validation. Xsight Labs uses a comprehensive set of tools to ensure we are delivering best-in-class networking switch silicon to our customers. Synopsys ZeBu Server 4 cloud solution is an integral element of our verification methodology, which has provided our verification team with conveni
Highlights:
Collaboration enables on-demand IC Validator physical signoff on Samsung SAFE Cloud Design Platform
Synopsys IC Validator cloud optimized technology enables massive scaling and efficient resource usage for fast design closure
Rescale and Microsoft Azure provide cloud-based, high-performance computing platform to instantly scale out computationally complex physical verification jobs
Synopsys, Inc. (Nasdaq: SNPS) today announced that its IC Validator physical verification solution has been deployed on Samsung s SAFE Cloud Design Platform (SAFE-CDP). This collaboration enables designers targeting Samsung Foundry advanced process nodes to achieve significant compute resource savings of up to 30 percent and faster signoff.
Mutual customers of Synopsys and Samsung Foundry can leverage IC Validator and Samsung Foundry process technology on the SAFE CDP platform, powered by the high-performance computing (HPC) resources from Rescale and Microsoft Azure. IC Validator,
Synopsys Extends Market Leadership in Verification Hardware with Performance and Enterprise Scalability Innovations
HAPS-100 Delivers 2x Higher Prototype Performance and 4x Higher Debug Performance for Software and Hardware Verification of Complex SoCs
News provided by
Share this article
Highlights:
Fastest performance for software development and system validation with 20-50 MHz for complex SoCs and up to 500 MHz for interface IP
Highest debug productivity through innovative system architecture with 4x signal capture and 4x higher debug performance
Enterprise and ecosystem scalability through HAPS Gateway software enabling multi-design, multi-user parallelization
Proven direct connect architecture leveraging largest prototyping ecosystem and broadest portfolio of interface cards
Synopsys Announces Euclide to Accelerate Design and Verification Productivity
Finds Bugs Early and Optimizes Code for Design Compiler, VCS and ZeBu
News provided by
Share this article
Highlights:
Correct-by-construction coding ensures RTL compatibility for Design Compiler and ZeBu
Real-time checks help to avoid costly testbench errors and increase VCS performance
Integration with Verdi for seamless debug and code development
Built-in SystemVerilog/UVM compliance assures best coding practices across verification teams
Synopsys, Inc. (Nasdaq: SNPS) today introduced Synopsys Euclide, the industry s next-generation hardware description language (HDL)-aware integrated development environment (IDE). Synopsys Euclide enables engineers to find bugs earlier and optimize code for design and verification flows by identifying complex design and testbench compliance checks during SystemVerilog and Universal Verification Methodology (UVM) development.