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Synopsys Announces Euclide to Accelerate Design and Verification Productivity
Finds Bugs Early and Optimizes Code for Design Compiler, VCS and ZeBu
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Highlights:
Correct-by-construction coding ensures RTL compatibility for Design Compiler and ZeBu
Real-time checks help to avoid costly testbench errors and increase VCS performance
Integration with Verdi for seamless debug and code development
Built-in SystemVerilog/UVM compliance assures best coding practices across verification teams
Synopsys, Inc. (Nasdaq: SNPS) today introduced Synopsys Euclide, the industry s next-generation hardware description language (HDL)-aware integrated development environment (IDE). Synopsys Euclide enables engineers to find bugs earlier and optimize code for design and verification flows by identifying complex design and testbench compliance checks during SystemVerilog and Universal Verification Methodology (UVM) development.