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Highlights: (PRNewsfoto/Synopsys, Inc.) DesignWare Controller, PHY and Verification IP supports the latest features in the PCI Express 6.0 specification, enabling early SoC development Low-latency controller with new MultiStream architecture delivers up to 2X the throughput of a conventional PCI Express controller High-performance PHY in 5-nm process with unique analog and DSP techniques provides 20 percent less power across chip-to-chip, riser card and backplane interfaces Comprehensive set of protocol, methodology and productivity features enable rapid verification of PCI Express 6.0 designs Synopsys, Inc. (Nasdaq: SNPS) today announced the industry s first complete IP solution for the PCI Express ® (PCIe ®) 6.0 technology that includes controller, PHY and verification IP, enabling early development of PCIe 6.0 system-on-chip (SoC) designs. Built on Synopsys widely deployed and silicon-proven DesignWare

John koeterSynopsys designwareKelly jamesPcie genJim pappasSilicon to softwareTechnology initiatives at intelSynopsys incDesignware controllerTechnology initiativesகெல்லி ஜேம்ஸ்ஜிம் பப்பச்சிலிக்கான் க்கு மென்பொருள்தொழில்நுட்பம் முயற்சிகள் இல் இன்டெல்சுருக்கம் இன்க்தொழில்நுட்பம் முயற்சிகள்