Synopsys Launches Industry's First Complete IP Solution for PCI Express 6.0 – EEJournal eejournal.com - get the latest breaking news, showbiz & celebrity photos, sport news & rumours, viral videos and top stories from eejournal.com Daily Mail and Mail on Sunday newspapers.
® EV Development Toolkit. By using Synopsys programmable ARC EV Processor, Kyocera successfully integrated high-performance artificial intelligence (AI) processing capabilities such as super resolution, with the flexibility to support future AI models. In addition, Kyocera deployed Synopsys HAPS
® FPGA-based prototyping system to accelerate ARC EV software development, SoC integration, and system validation. Implementing advanced AI functionality into our MFP SoC required high-performance, low-power processor IP with a high-quality tool chain, allowing us to find and test AI algorithms while developing the SoC in parallel, said Michihiro Okada, general manager, software development division at Kyocera Document Solutions Inc. Only Synopsys DesignWare ARC EV Processor IP and mature MetaWare EV Toolkit met our extensibility, performance, and area requirements.
January 28, 2021
Synopsys Demonstrates Silicon Proof of DesignWare 112G Ethernet PHY IP in 5nm Process for High-Performance Computing SoCs
DesignWare IP With Unmatched Long-Reach Performance Results Supports Insertion Loss Greater Than 40dB and Delivers Power-Efficiency of Less Than five pJ/Bit
MOUNTAIN VIEW, Calif., Jan. 28, 2021 /PRNewswire/ Synopsys, Inc. (Nasdaq: SNPS) today announced the silicon proof of DesignWare
® 112G Ethernet PHY IP in 5nm FinFET process, delivering significant performance, power and area advantages. The area-efficient DesignWare 112G Ethernet PHY enables designers to optimize highly dense system-on-chips (SoCs) with placement-aware IP that maximizes bandwidth per die-edge through stacking and placement on all four edges of the die. To extend performance, the DesignWare 112G PHY demonstrates zero bit-error rate post forward-error correction in greater than 40dB channels while offering power-efficiency of less than five picojoules per bit (pJ/bi
Highlights
® 5.0 or CXL™ 2.0 architectures
Pre-verified with DesignWare Controller IP for PCI Express technology and CXL enables fast integration and lowers risk
Efficient encryption/decryption and authentication with AES-GCM helps ensure data confidentiality and integrity for high-performance systems
Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of the DesignWare
® Integrity and Data Encryption (IDE) Security Modules to help designers protect against data tampering and physical attacks in high-performance computing (HPC) SoCs using the PCI Express
® (PCIe
™ (CXL
™) 2.0 interface. The DesignWare IDE Security Modules protect sensitive data with efficient encryption, decryption, and authentication based on AES-GCM algorithms while meeting PCIe 5.0 specification and CXL 2.0 IP performance and latency requirements. The DesignWare IDE Security Modules are designed to the latest PCIe 5.0 specification and CXL 2.0 interface standards and are designed an
January 27, 2021
Synopsys Delivers Industry’s First Integrity and Data Encryption Security IP Modules for PCI Express 5.0 and Compute Express Link 2.0 Specifications
DesignWare IDE Security IP Modules Protect Against Data Tampering and Physical Attacks in High-Performance Cloud Computing SoCs
MOUNTAIN VIEW, Calif., Jan. 27, 2021 /PRNewswire/
Highlights
® 5.0 or CXL™ 2.0 architectures
Pre-verified with DesignWare Controller IP for PCI Express technology and CXL enables fast integration and lowers risk
Efficient encryption/decryption and authentication with AES-GCM helps ensure data confidentiality and integrity for high-performance systems
Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of the DesignWare
® Integrity and Data Encryption (IDE) Security Modules to help designers protect against data tampering and physical attacks in high-performance computing (HPC) SoCs using the PCI Express