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eFPGA IP cores for GF 12LP/12LP+ Rad Hard By Design

Using Rad Hard By Design standard cells and design guidelines the silicon-proven EFLX eFPGA is now available, to US Companies, in a Rad Hard by Design . ....

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eFPGA Tile with power management for TSMC 40ULP & 40LP

The EFLX® 1K Logic IP tile is an eFPGA (embeddable FPGA) IP tile with power management containing 560 Look-Up-Tables (LUTs: each is 6-input, or dual-5-input, . ....

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DARPA adds RISC-V to its Toolbox: Defense researchers can get special access to SiFive chip designs

DARPA adds RISC-V to its Toolbox: Defense researchers can get special access to SiFive chip designs
theregister.com - get the latest breaking news, showbiz & celebrity photos, sport news & rumours, viral videos and top stories from theregister.com Daily Mail and Mail on Sunday newspapers.

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eFPGA IP cores for GF 22FDX

eFPGA IP cores for GF 22FDX
The EFLX®4K Logic IP core is an embeddable FPGA IP core containing 2,520 Look-Up-Tables (LUTs: each is 6-input, or dual-5-input, with 2 independent outputs with 2 bypassable flip flops) in Reconfigurable Building Blocks (RBBs) and 21 Kbit RAM, an improved XFLX™ interconnect network, multiple clocks & scan: fully reconfigurable in-field at any time.
The EFLX 4K DSP core has 40 DSP MACs (22x22 multiplier with 48 bit accumulator). In the Gen2 architecture, MACs cascade up to 10 stages without using the interconnect network.
Each EFLX core is a standalone embedded FPGA. Cores can be arrayed up to at least 8x8 to create arrays >500K LUT4s. Logic and DSP cores can be mixed. And RAM can be integrated as well. ....

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