Using Rad Hard By Design standard cells and design guidelines the silicon-proven EFLX eFPGA is now available, to US Companies, in a Rad Hard by Design .
For ASIC and SoCs designers who need fast, right-the-first time design and fast time to volume, Menta is unique in our ability to deliver proven eFPGAs .
The EFLX® 1K Logic IP tile is an eFPGA (embeddable FPGA) IP tile with power management containing 560 Look-Up-Tables (LUTs: each is 6-input, or dual-5-input, .
SPC (Synthesizable Programmable Core) is a soft FPGA core that is fully integrated into standard design flows and that allows the seamless implementation .