December 11, 2020
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The problem with assembling IP blocks onto a chip is that it can be hard to work out how they will interact with one another and the memory.
Whilst the IP blocks will have been pre-verified individually by the vendors, the key questions are how well they work together and, more importantly, how to optimise this. Sondrel has developed new enhanced workflow modelling tools for this purpose that reduce time to market, cut customer costs and optimise architectural design.
“Synopsys
® has a modelling tool called Platform Architect™ Ultra,” explained Paul Martin, Head of Architecture at Sondrel. “Its ‘Fast Timed’ IP blocks reveal details of how data is moving on the chip between them, and back and forth to the off- and on-chip memory. We have developed enhanced versions of the Workflow Modelling blocks with the co-operation of Synopsys. These enable us to create accurate transaction models so that we can see exactly how the data moves throu