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Tweaking parameters on a simulation model to judge final performance spec

Typically, verication is done by synthesising RTL and running it to see how well it performs against the performance specification that were defined at the

Synopsys systemSynopsys verdiPerformance verification environmentSynopsys systemcExploration platformSystemc simulationSystem architectPerformance engineersSystem verilog

Sondrel develops Performance Verification Environment to fast-track ASIC creation

Sondrel develops Performance Verification Environment to fast-track ASIC creation
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Synopsys systemSynopsys verdiPerformance verification environmentSynopsys systemcExploration platformMentor questaSystemc simulationSystem architectPerformance engineersSystem verilog

Sondrel cuts verification time with new, enhanced, work flow modelling tools – CIE

December 11, 2020 529 Views The problem with assembling IP blocks onto a chip is that it can be hard to work out how they will interact with one another and the memory. Whilst the IP blocks will have been pre-verified individually by the vendors, the key questions are how well they work together and, more importantly, how to optimise this. Sondrel has developed new enhanced workflow modelling tools for this purpose that reduce time to market, cut customer costs and optimise architectural design. “Synopsys ® has a modelling tool called Platform Architect™ Ultra,” explained Paul Martin, Head of Architecture at Sondrel. “Its ‘Fast Timed’ IP blocks reveal details of how data is moving on the chip between them, and back and forth to the off- and on-chip memory. We have developed enhanced versions of the Workflow Modelling blocks with the co-operation of Synopsys. These enable us to create accurate transaction models so that we can see exactly how the data moves throu

Paul martinPlatform architectFast timedWorkflow modellingPerformance verification environmentபால் மார்டின்நடைமேடை கட்டட வடிவமைப்பாளர்வேகமாக நேரம் முடிந்ததுபணிப்பாய்வு மாடலிங்செயல்திறன் சரிபார்ப்பு சூழல்