Cadence Design Systems, Inc.
Cadence Unveils Next-Generation Palladium Z2 and Protium X2 Systems to Dramatically Accelerate Pre‑Silicon Hardware Debug and Software Validation
Tuesday, April 6, 2021 1:54PM IST (8:24AM GMT)
Highlights:
New dynamic duo delivers 2X capacity and 1.5X higher performance compared to previous-generation Palladium Z1 and Protium X1 systems
Palladium Z2 emulation based on a new custom emulation processor offers fastest, most predictable compiles and most comprehensive pre-silicon hardware debug capabilities
Protium X2 prototyping based on latest Xilinx UltraScale+ VU19P FPGAs offers highest performance and fastest bring-up times for pre-silicon software validation of billion-gate designs
Cadence provides the most comprehensive solution for IP and SoC verification, hardware and software regressions, and early software development
April 6, 2021
Cadence Unveils Next-Generation Palladium Z2 and Protium X2 Systems to Dramatically Accelerate Pre-Silicon Hardware Debug and Software Validation
Highlights:
New dynamic duo delivers 2X capacity and 1.5X higher performance compared to previous-generation Palladium Z1 and Protium X1 systems
Palladium Z2 emulation based on a new custom emulation processor offers fastest, most predictable compiles and most comprehensive pre-silicon hardware debug capabilities
Protium X2 prototyping based on latest Xilinx UltraScale+ VU19P FPGAs offers highest performance and fastest bring-up times for pre-silicon software validation of billion-gate designs
Cadence provides the most comprehensive solution for IP and SoC verification, hardware and software regressions, and early software development
Cadence Unveils Next-Generation Palladium Z2 and Protium X2 Systems
Cadence Design Systems, Inc. announced the Cadence® Palladium® Z2 Enterprise Emulation and Protium™ X2 Enterprise Prototyping systems to handle the exponentially increasing system design complexity and time-to-market pressures. Building upon Cadence’s current industry-leading Palladium Z1 emulation and Protium X1 prototyping platforms, these next-generation systems enable the highest throughput pre-silicon hardware debug and pre-silicon software validation for the industry’s largest multi-billion-gate system-on-chip (SoC) designs. Dubbed the Cadence “dynamic duo” for its tight integration with unified compiler and interfaces, the next-generation emulation processors and Xilinx UltraScale+ VU19P FPGAs in these systems provide customers with 2X capacity and 1.5X performance improvements over their predecessors, allowing Cadence customers t