Cadence Unveils Next-Generation Palladium Z2 and Protium X2 Systems
Cadence Design Systems, Inc. announced the Cadence® Palladium® Z2 Enterprise Emulation and Protium™ X2 Enterprise Prototyping systems to handle the exponentially increasing system design complexity and time-to-market pressures. Building upon Cadence’s current industry-leading Palladium Z1 emulation and Protium X1 prototyping platforms, these next-generation systems enable the highest throughput pre-silicon hardware debug and pre-silicon software validation for the industry’s largest multi-billion-gate system-on-chip (SoC) designs. Dubbed the Cadence “dynamic duo” for its tight integration with unified compiler and interfaces, the next-generation emulation processors and Xilinx UltraScale+ VU19P FPGAs in these systems provide customers with 2X capacity and 1.5X performance improvements over their predecessors, allowing Cadence customers to run more validation cycles on bigger chips in less time. Additionally, both systems offer breakthrough modular compile technology capable of compiling 10 billion gates in under 10 hours on the Palladium Z2 system and in under 24 hours on the Protium X2 system.