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Cadence Unveils Joules RTL Design Studio, Delivering Breakthrough Gains in RTL Productivity and Quality of Results

Highlights: Delivers up to 5X faster RTL convergence and up to 25% improved QoR RTL designers can rapidly get accurate insight into physical effects and actionable guidance on improving RTL Integrates with Cadence Cerebrus, and Cadence JedAI Platform for AI-driven RTL optimization

Shunji katsukiHarrison hsiehChin chi tengMark galbraithCadence design systems incDigital signoff group at cadenceGlobal development groupSilicon product developmentCompanies to workSoc system development divisionCadence design systemsCadence joulesBusiness wireImplementation systemSynthesis solutionIntelligent chip explorer

Cadence Unveils Joules RTL Design Studio, Delivering Breakthrough Gains in RTL Productivity and Quality of Results

Cadence Unveils Joules RTL Design Studio, Delivering Breakthrough Gains in RTL Productivity and Quality of Results

Chin chi tengHarrison hsiehShunji katsukiCadence design systemsDigital signoff group at cadenceGlobal development groupSoc system development divisionSilicon product developmentCadence joulesInnovus implementation systemSynthesis solutionCerebrus intelligent chip explorerCadence joint enterprise dataSignoff groupIntelligent system designGenus synthesis solution

Cadence Revolutionizes Verification Productivity with the Verisium AI-Driven Verification Platform – Consumer Electronics Net

Cadence Revolutionizes Verification Productivity with the Verisium AI-Driven Verification Platform – Consumer Electronics Net
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Cadence Cerebrus Delivers Transformative Results on Next-Gen Designs

Cadence Cerebrus Delivers Transformative Results on Next-Gen Designs
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Chin chi tengHarrison hsiehDigital signoff group at cadenceSilicon product development at mediatekCadence design systemsDesign systemsCadence cerebrus intelligent chip explorerCadence cerebrusSignoff groupSilicon product development

Cadence Cerebrus AI-Based Solution Delivers Transformative Results on Next-Generation Customer Designs

Highlights: • MediaTek shrinks die area by 5% and reduces power by more than 6% with the Cadence Cerebrus floorplan optimization feature • Cadence collaborates with Renesas to deploy Cadence Cerebrus on two designs; achieves better performance on an advanced-node CPU design and a leakage power reduction on an MCU design SAN JOSE, Calif., June…

Chin chi tengHarrison hsiehToshonori inoshitaDigital signoff group at cadenceRenesas electronics corporationSilicon product development at mediatekCadence design systems incCadence cerebrusCadence design systemsIntelligent chip explorerSignoff groupSilicon product developmentRenesas electronicsImplementation systemSynthesis solutionTiming signoff solution