SAN FRANCISCO – Dec. 16, 2021 – CEA, in collaboration with CNRS Néel, a leading team in Si-based quantum computing, presented two papers on that topic at
IBM revealed vertical FET CMOS logic at a sub-45nm gate pitch on bulk silicon wafers at the IEEE International electron devices meeting in San Francisco th
In recent years, lanthanum aluminate/strontium titanate (LAO/STO) heterointerfaces have been used to create a growing family of nanoelectronic devices based on nanoscale control of LAO/STO metal-to-insulator transition. The properties of these devices are wide-ranging, but they are restricted by nature of the underlying thick STO substrate. Here, single-crystal freestanding membranes based on LAO/STO heterostructures were fabricated, which can be directly integrated with other materials via van der Waals stacking. The key properties of LAO/STO are preserved when LAO/STO membranes are formed. Conductive atomic force microscope lithography is shown to successfully create reversible patterns of nanoscale conducting regions, which survive to millikelvin temperatures. The ability to form reconfigurable conducting nanostructures on LAO/STO membranes opens opportunities to integrate a variety of nanoelectronics with silicon-based architectures and flexible, magnetic, or superconducting materi