Ethernet & CPRI PCS 1G/2.5G/5G/10G/25G Comcores offers a PCS IP core that can be used for both Ethernet and CPRI. Comcores PCS Ethernet and CPRI IP core is a silicon agnostic implementation of the PCS layer compliant with Ethernet standard IEEE 802.3-2015 and CPRI Specification V7.0. The IP-core supports 1G, 2.5G, 5G, 10G, and 25G Ethernet data rates as well as CPRI data rate option 1 (614.14M) to option 10 (24.33024G). Comcores PCS Ethernet and CPRI IP core can be dynamically configured to enable either 8B/10B or 64B/66B encoding/decoding.
In order to ensure easy integration, build-in test capabilities are provided in the core. The IP-core has been optimized for size and is a highly tested solution that will fast track any project
Comcores PCS IP core is a silicon agnostic implementation of the PCS layer compliant with Ethernet standard IEEE 802.3-2015. The IP-core supports 1G and .
PCI Express 4.0/3.0/2.1/1.1 Support The Northwest Logic Expresso 4.0 Core is part of Rambus’ PCI Express Solution. This solution is designed to achieve maximum PCI Express throughput while being easy to use.
The Expresso 4.0 Core separately, or in combination with Northwest Logic family of DMA Cores and DMA Drivers, provide the maximum system throughput on a PCI Express link. Contact Rambus for more details.
The core is specifically designed for ease of use including full receive packet decoding, complete error handling, automatic handling of PCI Express message packets and comprehensive system-debug and link monitoring support.
The core is delivered fully integrated and verified with the user’s Target PHY. Contact Rambus for a complete list of supported PHYs. To accelerate simulations, the core is also delivered integrated with a fast-simulating behavioral PHY.
USB 2.0 femtoPHY in Samsung (14nm, 11nm, 8nm, 7nm, 5nm) The Synopsys DesignWare® USB 2.0 femtoPHY provides designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer applications such as smartphones, tablets, digital TVs, and media players. Offering reduced silicon cost and longer battery life, the DesignWare USB 2.0 femtoPHY IP delivers 50% smaller die area and minimizes active and suspend power consumption.
The DesignWare USB 2.0 femtoPHY implements the latest USB battery charger version 1.2 and USB On-The-Go (OTG) version 2.0 specifications from the USB Implementer’s Forum (USB-IF).
Architected for the industry’s most advanced 1.8V process technologies, the USB 2.0 femtoPHY is designed with features created to minimize effects due to variations in foundry process, device models, packages, and board parasitics.
Low Drop 50mA Regulator The S3REG5018T12FFC is a regulator circuit which has been designed to provide 1.8V with a load current of up to 50mA. The output voltage is programmable.
The S3REG5018T12FFC is a regulator circuit that features an automatic feedback sensing option to maintain a constant regulated output voltage level. It has been designed to provide a stable output in both low-drop and high-drop
operation, while maintaining minimum ripple on supply lines in the presence of large load current spikes inherent with switching loads, e.g. high-speed ADCs.
The S3REG5018T12FFC has been designed to allow low-drop operation (the PMOS pass device has been scaled for a voltage drop of 200mV). To achieve these goals, the S3REG5018T12FFC requires a 1μF external ceramic