DPA Resistant Cryptographic Accelerator Core ChaCha20 – Fast Rambus DPA Resistant Hardware Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA. ChaCha 20 Fast DPA resistant cryptographic accelerator core.
The DPA Resistant Hardware cores offer chipmakers an easy-to-integrate technology-independent soft-macro security solution with built-in side-channel resistance for cryptographic functions across a wide array of devices.
These high-performance cores provide a higher level of protection than standard security cores, while improving time-to-market, as all the cores are validated DPA countermeasures. It is highly flexible for integration with standard cipher modes such as Cipher Block Chaining (CBC), Counter (CTR) and Authenticated Encryption mode / Galois Counter (GCM) modes. The fast AES core performs AES encryption with DPA protection using only 2 clock cycles per AES round, outperforming any existin
AES Key Wrap Accelerator The EIP-37 is the IP for accelerating the AES Key Wrap cipher algorithm (NIST-Key-Wrap & RFC3394). Designed for fast integration, low gate count and full transforms, the EP-37 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into SoCs that need high speed key wrap and (key) storage or key import and export systems View see the entire get in contact with AES IP
INSIDE Secure SM3 Engine The EIP-52 SM3 Engine implements the SM3 hash algorithm. The accelerators include I/O registers, hash calculation cores, message padding logic, and data scheduling logic. Designed for fast integration, low gate count, and maximum performance, the SM3 Engine provides a reliable and cost-effective SM3 IP solution that is easy to integrate into SoC designs. View see the entire get in contact with Sm3 IP
Voltage Optimization Modules Two patented IPs and a design methodology to estimate and track the minimum supply voltage (Vmin) for each individual circuit in the field: TMFLT-S IP (Timing Fault Sensor)
Estimates the Fmax/Vmin of the circuit during a calibration phase TMFLT-R IP (Timing Fault Ring) :
Tracks either the minimum voltage operation (Vmin) or the maximum clock frequency (Fmax) during run-time phase TMFLT Sensor implementation methodology:
Allows choosing the best register candidates to insert TMFLT Sensors. Allowing to minimize the area overhead to less than 2%. View see the entire