1-32Gbps PCI-Express Gen1 - Gen5 PHY and CXL SerDes The Alphawave PipeCORE PHY IP is a high-performance, low-power, low latency PCIe Gen1 – Gen6 and CXL PHY, that supports both NRZ and PAM4 modulation. It includes a hardened PMA layer and a soft PCS layer deliverable. The PipeCORE is based on the industry leading AlphaCORE DSP architecture. The PipeCORE is power and performance optimized for the strenuous challenges of PCIe and is targeted to deliver unparalleled bandwidth for the next generation of computing interfaces and optimized for low latency CXL applications.
Targeted for 45+dB of channel loss for PCIe Gen 1 – Gen5 NRZ rates, the PipeCORE delivers a power-optimized, physical layer IP that yields more than 400Gbps of data throughput per millimeter of Silicon perimeter.
Distributed Thermal Sensor (DTS) Deep NWELL, TSMC N5 The highly granular DTS offers a significant area reduction in comparison to some standard in-chip thermal sensor solutions and supports high accuracy measurement across a wide temperature range at enhanced conversion speeds. Thermal activity can be unpredictable and if not monitored carefully can cause over-heating and excessive power consumption which in turn impacts device longevity. The ability to make precise thermal measurements beside or within CPU cores, high speed interfaces or highly active circuitry has become a mandatory requirement for devices used within a range of application areas. View see the entire
Boot Protection Pack / Root-of-Trust The Boot Protection Pack is a solution provided by Secure-IC to ensure a Secure Boot function. The Boot Protection Pack provides a secure root-of-trust with a high level of resistance against malevolent attacks. It ensures integrity of the SoC security features, guarantees that the firmware is genuine and ensures a secure firmware update.
Boot Protection Pack ensures secure boot functionality. The boot sequence is started when the system is turned on, the processor loads and executes a first set of instructions from an internal NVM. This first set of instructions is called bootloader and it is used to initialize Intellectual Property (IP) cores and peripherals of Securyzr sub-system and to enable the transfer of the software which is held in an external NVM to an internal Volatile Memory (VM). To prevent the system from malwares, which are mainly injected through a modification of the Operating System (OS) and the application code, the Boot
Low-power HMAC SHA AES Accelerator The HMAC SHA AES Accelerator is a low-power low-gate count crypto core with DMA capability and local key storage. Compared to a software only solution, the core provides higher performances and additional security to applications.
By using dedicated hardware accelerators, the HMAC SHA AES Accelerator provides a first performance boost compared to software execution on the host processor. The second advantage is the ability to store keys in an integrated RAM via DMA, and keep these inaccessible, but usable, for the host/application.
The HMAC SHA AES Accelerator provides hardware cryptographic algorithm implementations for optimal performance, user experience, battery lifetime and robust security.
CC-100IP-RF Analog and RF Sensitivity Enhancement IP The CC-100IP-RF is a RF and Analog Frontend Sensitivity Enhancement IP Block that embeds a Hyper-Capacitor with a Capacitance Multiplication, Series Inductance Nullification, Cybersecurity Enhancement and Energy Harvesting capabilities. The IP accomplishes Signal Sensitivity Enhancment by improving the PSRR of sensitive RF and Analog front end receivers. CC-100IP-RF Hyper-Bypass Capacitor creates an adjustable Impedance controlled point in IC power grids aiding in maximum on chip supply line filtering, Impedance matching for Power Grid flat frequency response, showing an up to a 600X improvement in effective and reservoir capacitance. The IP features a circuit noise activated dynamic input current controlled reservoir capacitance, and can function as a “stand-alone” on Chip DCAP, or work in parallel with existing DCAP structures. Due to the embedded IP negative feedback, the CC-100 features a 25% reduction in Hyper-Capa