Chemical mechanical polishing (CMP) – also known as planarization – has long been the most commonly employed technique for smoothing and flattening wafer surfaces during the fabrication of semiconductor integrated chips (IC). This approach has been common practice for decades.
During this time, post-CMP evaluation has become the standard means of ensuring adequate planarity of IC layers, as well as the most common approach to confirming their compliance with planarity requirements.
Conventional post-CMP process evaluation methods have analytical limitations, however. Ever tightening process control limits have led to an increasing need for improved accuracy in the wafer surface characterization methods used in semiconductor chip manufacturing.