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Where now for the transistor?

Researchers to Showcase 25 nm iPMA Hexa-MTJ Technology for Scalable eFlash Type STT-MRAM

Researchers to Showcase 25 nm iPMA Hexa-MTJ Technology for Scalable eFlash Type STT-MRAM
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Researchers to Showcase 25 nm iPMA Hexa-MTJ Technology for Scalable eFlash Type STT-MRAM

Researchers to Showcase 25 nm iPMA Hexa-MTJ Technology for Scalable eFlash Type STT-MRAM
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A question of scale

A question of scale Is Moore s Law dead, dying or in rude health? It depends who you ask. In turn, it depends on how they are applying the ruler when it comes to measuring the scaling factors as semiconductor processes move down the nanometre curve. Together with colleagues from MIT, TSMC, UC Berkeley and his own institution, Philip Wong, professor of electrical engineering at Stanford University, wrote a paper for April s Proceedings of the IEEE on the progress made by silicon scaling and used it as the basis for his keynote at July s Design Automation Conference. In their view, Moore’s Law is still in operation but the assumptions that underpin it have changed. As a result, technologists should look far less at simple areal scaling of transistor footprints and spacing but take a view on the effective density of each successive node.

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