At this week’s 2022 IEEE VLSI Symposium on Technology and Circuits, imec is presenting the first experimental demonstration of a routing scheme for logic ICs with backside power delivery enabled through nano-through-silicon-vias (nTSVs) landing on buried power rails (BPRs).
Highlights: • Integrity 3D-IC integrates design planning, implementation and system analysis in a single, unified cockpit • Designers can achieve system-driven PPA through the availability of integrated thermal, power and static timing analysis capabilities • Cadence’s third-generation 3D-IC solution supports a wide range of application areas including, hyperscale computing, consumer, 5G communications, mobile and automotive…