Comprehensive IP portfolio on 3nm chiplet-enabled platform accelerates movement of massive AI-generated data in compute, memory, and networking infrastructure
SAN JOSE, Calif., April 24, 2023 Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the tapeout of Cadence® 16G UCIe™ 2.5D advanced package IP on TSMC’s 3nm (N3E) process technology. Implemented on TSMC’s 3DFabric™ CoWoS-S silicon interposer technology, the IP offers ultra-high bandwidth density, efficient low-power performance and superior low latency, making it ideal for…
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As Synopsys and TSMC collaborate to deliver high-quality IP on TSMC’s advanced FinFET processes, Synopsys announces a successful tape-out of the Universal .