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The Digital Blocks DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory .

Digital blocksMulti channel scatter gatherStream interfacesStatus streamAxi4 stream interfaceXi4 memory mapDma controllerMa axi4 stream to from memory map scatter gather command listB dmac mc2 cs mm2s s2mmP coreIlicon ipEmiconductor ip