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Fractional-N Frequency Synthesizer PLL (3nm


Fractional-N Frequency Synthesizer PLL (3nm - 180nm)
Widely programmable fractional-N delta sigma frequency synthesizer. Low Power/ Low Area hard macro with industry leading jitter performance for its power/area class.
Product is currently in mass production from 5nm to 180nm, and ready now in 3nm.
Integer-only, DDR/multi-phase, LC and low-jitter ring PLLs also available.
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Block Diagram of the Fractional-N Frequency Synthesizer PLL (3nm - 180nm)
Fractional-N Frequency Synthesizer PLL
IP ....

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RBG DPA resistant cryptographic accelerator core


RBG DPA resistant cryptographic accelerator core
Rambus DPA Resistant Cryptographic Accelerator Core RBG (NRBG+DRBG) prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA. RBG DPA resistant cryptographic accelerator core.
The DPA Resistant Hardware cores offer chipmakers an easy-to-integrate technology-independent soft-macro security solution with built-in side-channel resistance for cryptographic functions across a wide array of devices.
These high-performance cores provide a higher level of protection than standard security cores, while improving time-to-market, as all the cores are validated DPA countermeasures. It is highly flexible for integration with standard cipher modes such as Cipher Block Chaining (CBC), Counter (CTR) and Authenticated Encryption mode / Galois Counter (GCM) modes. The fast AES core performs AES encryption with DPA protection using only 2 clock cycles per AES round, outperfo ....

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GDDR6 Controller


GDDR6 Controller
Northwest Logic GDDR6 Controller Core from Rambus is designed for use in applications requiring high memory throughput, high clock rates and full programmability.
The core accepts commands using a simple local interface and translates them to the command sequences required by GDDR6 SGRAM devices. The core also performs all initialization, refresh and power-down functions.
The core uses bank management techniques to monitor the status of each GDDR6 SGRAM bank (up to 16 banks managed concurrently). Banks are only opened or closed when necessary, minimizing access delays.
The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput. ....

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