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TESIC CC EAL5+ Secure Element IP Core TESIC is a CC EAL5+ PP0084 proven/certification-ready secure element IP that is delivered as hard macro for plug-and-play System-on Chip (SoC) integration View see the entire get in contact with Block Diagram of the TESIC CC EAL5+ Secure Element IP Core secure element IP ....
GDDR6 PHY&Controller Samsung 10/8LPP The Innosilicon GDDR6 PHY is the world’s first silicon proven commercial GDDR6 IP, which is fully compliant with the JEDEC GDDR6 (JESD250) standard, supporting up to 16Gbps per pin. The GDDR6 interface supports 2 channels, each with 16bits for a total data width of 32bits. With speed up to 16Gbps per pin, the Innosilicon GDDR6 PHY offers a maximum bandwidth of up to 64GB/s. And, the Innosilicon GDDR6X PHY uses four-level pulse amplitude modulation (PAM4) signaling to extract more efficiency and higher data rates, which will be available in advanced FinFET nodes for leading-edge customer integration. ....
Reorder Core The Reorder Core from Rambus reorders requests based on first on priority and second on throughput optimization. Throughput optimization includes moving same bank/same row requests next to each other, same bank/ different row requests away from each other, moving reads next to reads and write next to writes. The core can be used to optionally enforce data coherency by preventing any same row requests from passing over each other. The core can also optionally disable intra-port (within a port) reordering. Disabling intra-port reordering ensures that the requests on each port are always executed in the same order. In this case only inter-port (between ports) reordering is allowed. The core can be used in a single port mode or a multi-port mode in conjunction with Northwest Logic Multi-Port Front- End Core. ....
High Performance DDR4/3 Memory Controller Mobiveil s DDR4/3 Memory Controller is a highly flexible and configurable design targeted for high performance enterprise server and real-time consumer applications that utilize computational elements like graphics controllers, general purpose, digital signal processors, etc. The controller architecture is carefully tailored to achieve reliable high-frequency operation, dynamic power management, error injection and support for rapid system debug. DDR4/3 Controller is part of Mobiveil’s Storage and Memory controller family of IP solutions which also includes LPDDR2/3, UNEX, IFC, and eSDHC IP cores. The controller s simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible AXI System ....
DVB-S2X WideBand Demodulator IP This is a high-performance, dual high-symbol-rate (HSR) DVB-S2/S2X demodulator IP extarcted from production chipsets with integrated tuner and silcon proven technology. The demodulators are compliant with Annex M of the DVB-S2 specification EN 302 307 and can demodulate signals up to 500 Msymbol/s. Each HSR demodulator may demodulate up to 2 slices. This implements 8 multi-standard demodulators capable of DVB-S, DTV legacy, DVB-S2 and DVB-S2X broadcast-profile signal processing. This IP incorporates a high-speed DVB-S2 forward error corrector (FEC) which is designed to handle up to 720 Mchannel-b/s at its input. This allows for 8 simultaneous 8PSK decodes at 30 Msymbol/s. This capacity is shared between the demodulators and may be allocated at will, provided that the maximum capacity limit is not exceeded.This IP features four integrated full-band capture tuners which cover the band 950 to 2150 MHz. The signal is sampled by high-perfo ....