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A RISC-V REVOLUTION: The Rise of Free and Open-Source Silicon for Makers

Born at the same university as the original, RISC-V is Berkeley’s fifth-generation RISC architecture

United statesSteve furberVikay krishnanTeo swee annStefan wallentowitzEben uptonTensilica xtensaDavid pattersonStarfive visionfiveKrste asanoviSophie wilsonRiscv internationalBouffalo labWestern digitalGreenwaves technologiesEspressif systems

European Processor Initiative samples first chips

European Processor Initiative samples first chips
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United kingdomComunidad autonoma de catalunaAtmanirbhar bharatStefan wallentowitzRiscv internationalEuropean processor initiativeBarcelona supercomputing centreUniversity of zagrebFossi foundationFoundation for researchEuropean unionEuropean union highV based european processor acceleratorTensor acceleratorஒன்றுபட்டது கிஂக்டம்காமுனிடட தன்னாட்சி டி கடலுள்

Chinese chipmakers look to topple Arm s Cortex-A76 with XiangShan RISC-V design

Chinese chipmakers look to topple Arm s Cortex-A76 with XiangShan RISC-V design
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Bao yungangYinan xuStefan wallentowitzResearch centre of advanced computer systemsMicrocore corporationInstitute of computing technologyMulan permissive software licenceChinese communist partyChinese academy of sciencesFossi foundationComputing technologyChinese academyDebian linuxBeijing microcore corporationResearch centreAdvanced computer systems

Deep neural networks IN SPAAACE: Vector-enhanced RISC-V chips could give satellites onboard AI

Deep neural networks IN SPAAACE: Vector-enhanced RISC-V chips could give satellites onboard AI
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Cobham gaislerJiri gaislerStefan wallentowitzFossi foundationEuropean space researchEuropean space agencyJournal of aerospace information systemsTechnology centreDelft university of technology tuDelft universityAerospace information systemsஐரோப்பிய இடம் ஆராய்ச்சிஇதழ் ஆஃப் விண்வெளி தகவல் அமைப்புகள்தொழில்நுட்பம் மையம்டெல்ஃப்ட் பல்கலைக்கழகம் ஆஃப் தொழில்நுட்பம் துடெல்ஃப்ட் பல்கலைக்கழகம்

TimeCache aims to block side-channel cache attacks – without hurting performance

TimeCache aims to block side-channel cache attacks – without hurting performance
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Divya ojhaSean wrightStefan wallentowitzInternational symposium on computer architectureFossi foundationUniversity of rochesterProfessor at munich university of applied sciencesUniversity of rochester department computer scienceSandhya dwarkadasComputer scienceAnnual international symposiumComputer architectureMunich universityApplied sciencesFusing timeEliminate cache side channels