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Foundry Wars Begin

Foundry Wars Begin
Intel’s re-entry has kicked the competition into high gear, with massive spending on equipment and new fabs.
Leading-edge foundry vendors are gearing up for a new, high-stakes spending and technology race, setting the stage for a possible shakeup across the semiconductor manufacturing landscape.
In March, Intel re-entered the foundry business, positioning itself against Samsung and TSMC at the leading edge, and against a multitude of foundries working at older nodes. Intel announced plans to build two new fabs with a capital spending budget set at $20 billion in 2021.
Earlier this month, TSMC responded by raising the ante, increasing its capital spending budget to $30 billion, up from $28 billion in its previous forecast. In total, TSMC plans to spend $100 billion over the next three years. TSMC, Samsung and others also are building new fabs. These announcements are reminiscent of events more than a decade ago, when foundries were involved in a ....

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Petaflop era for semiconductor manufacturing

Petaflop era for semiconductor manufacturing
January 29, 2021 //
By Nick Flaherty
Computational Design Platform from DS2 with Nvidia A40 GPU achieves 1.8 PFLOPS for designing masks
D2S has launched its seventh generation of its computational design platform (CDP) for designing the complex masks for chip making.
The CDP uses Nvidia’s latest GPU chips to reach petaflop performance for 5nm and 3nm manufacturing. This is used for the calculations for inverse lithography technology (ILT) to produce curvilinear shapes on photomasks, mask process correction (MPC) for multibeam mask writing to process these incredibly complex mask shapes, curvilinear mask and wafer simulation and verification, and deep learning for photomask and semiconductor manufacturing. The GPU performance is particularly important for curvilinear shapes, which are not possible with CPU-only applications. ....

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D2S Unleashes the Petaflops Computing Era for Semiconductor Manufacturing

D2S Unleashes the Petaflops Computing Era for Semiconductor Manufacturing
Latest-generation Computational Design Platform with NVIDIA A40 GPU Achieves 1.8 PFLOPS
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SAN JOSE, Calif., Jan. 26, 2021 /PRNewswire/ D2S, a supplier of GPU-accelerated solutions for semiconductor manufacturing, today introduced the seventh generation of its computational design platform (CDP), a scalable processing solution for simulation-based semiconductor design and manufacturing applications. D2S CDPs are architected to ensure the high speed, accuracy and reliability required for 24x7 cleanroom production environments. Powered by NVIDIA Ampere architecture-based A40 GPUs, the D2S seventh-generation CDP achieves more than 1,800,000,000,000,000 floating point operations per second (1.8 PFLOPS) of single precision (SP) processing speed per rack. D2S has already received multiple orders for the seventh-generation CDP, bringing the ....

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New Transistor Structures At 3nm/2nm

New Transistor Structures At 3nm/2nm
Gate-all-around FETs will replace finFETs, but the transition will be costly and difficult.
Several foundries continue to develop new processes based on next-generation gate-all-around transistors, including more advanced high-mobility versions, but bringing these technologies into production is going to be difficult and expensive.
Intel, Samsung, TSMC and others are laying the groundwork for the transition from today’s finFET transistors to new gate-all-around field-effect transistors (GAA FETs) at the 3nm and 2nm nodes, starting either next year or in 2023. GAA FETs hold the promise of better performance, lower power, and lower leakage, and they will be required below 3nm, when finFETs run out of steam. But even though these newfangled transistors are considered an evolutionary step from finFETs, and they have been in R&D for years, any new transistor type or material is a huge undertaking for the chip industry. Chipmakers have ....

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Blog Review: Dec. 23

Blog Review: Dec. 23
Cadence’s Paul McLellan checks out how Arm is becoming a powerhouse in the server and high-end space with the addition of new R&D and a focus on getting the most out of its architecture.
Siemens EDA’s Harry Foster continues his look at verification trends in FPGAs by checking out adoption of different simulation and formal technologies.
Synopsys’ Taylor Armerding looks ahead to 2021 with some predictions from exports on the state of software security, including the risks of social engineering and ransomware, cloud adoption, and low-code/no-code platforms.
Arm’s Ambroise Vincent introduces the Morello security architecture based on Capability Hardware Enhanced RISC Instructions (CHERI) and how to extend Memory Model Tools to include Morello and increase the coverage of the tools. ....

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