Highlights: (PRNewsfoto/Synopsys, Inc.) DesignWare Controller, PHY and Verification IP supports the latest features in the PCI Express 6.0 specification, enabling early SoC development Low-latency controller with new MultiStream architecture delivers up to 2X the throughput of a conventional PCI Express controller High-performance PHY in 5-nm process with unique analog and DSP techniques provides 20 percent less power across chip-to-chip, riser card and backplane interfaces Comprehensive set of protocol, methodology and productivity features enable rapid verification of PCI Express 6.0 designs Synopsys, Inc. (Nasdaq: SNPS) today announced the industry's first complete IP solution for the PCI Express ® (PCIe ®) 6.0 technology that includes controller, PHY and verification IP, enabling early development of PCIe 6.0 system-on-chip (SoC) designs. Built on Synopsys' widely deployed and silicon-proven DesignWare