May 25, 2021
Avery Design Launches PCI Express 6.0 Verification IP to Enable Early Development, Compliance Checking for New Version of Standard
Tewksbury, MA – May 25, 2021 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of major updates to the company’s flagship PCI Express® (PCIe®) 6.0 and PIPE 6.0 VIP solution. Avery unveiled the solution at the PCI-Sig DevCon event this week.
The solution supports the latest features and capabilities in the high-speed interconnect protocol, including a doubling of data rates compared to PCIe 5.0, to 64 GT/s speeds, its move to PAM4 encoding and FLIT mode, the introduction of low latency FEC, and backwards compatibility with all previous specification versions.
PCI Express Gen1/Gen2/Gen3 Hybrid Controller with SRIOV Support The PCI Express Hybrid (RC and EP) Controller is a highly flexible and configurable design targeted for end-point implementations in desktop, server, mobile, networking and telecom applications. The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption, and silicon footprint.
The PCI Express Hybrid (RC and EP) Controller is part of the PCI-Express (GPEX) family of IP solutions which includes Endpoint (GPEX-EP), Root Complex (GPEX-RC), Switch port Controller (GPEX-SW), Switch (GPEX-SWITCH), GPEX-AXI Bridge (GPEX-AXI), GPEX-AHB Bridge (GPEX-AHB) and Advanced Switching (GPEX-AS) designs.
The controller s simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Sta