Imperas Expands Partnership with Valtrix to Address Growing RISC-V Verification Market eejournal.com - get the latest breaking news, showbiz & celebrity photos, sport news & rumours, viral videos and top stories from eejournal.com Daily Mail and Mail on Sunday newspapers.
Imperas updates RISC-V verification software
The latest addition to the Imperas RISC-V Verification IP (VIP) software has Floating-Point architectural validation test suites covering the RISC-V Specifications for 32bit Single-Precision (32F), 64bit Single-Precision (64F), and 64bit Double-Precision (64D).
These tests extend the current Imperas range of tests for ratified and near-ratified specifications tests.
The latest RISC-V verification ‘step-and-compare’ methodology can be used to verify an RTL processor implementation against the Imperas golden reference model in a SystemVerilog UVM environment.
This covers asynchronous events and offers a transition to debug analysis when an issue is found. More details on test benches with Imperas RISC-V verification reference models are available at https://www.imperas.com/riscv.
Imperas extends RISC-V processor verification ecosystem Imperas Software, a specialist in RISC-V processor verification technology, has announced the latest addition to its suite of RISC-V Verification IP (VIP) solutions.
This solution includes Floating-Point architectural validation test suites covering the RISC-V Specifications for 32bit Single-Precision (32F), 64bit Single-Precision (64F), and 64bit Double-Precision (64D).
The tests are designed to extend the company s current range of tests for ratified and near-ratified specifications tests, and complement the de facto industry adoption of the Imperas RISC-V verification reference model.
Processor verification is the essential focus of any development team. Design bugs that are caught early help projects complete on schedule. The impact of late-stage bugs, and associated costs, can be significant.
Imperas Leads The RISC-V Processor Verification Ecosystem
Verification IP extended with Floating-Point architectural validation test suites based on golden reference model and coverage-based development.
Oxford, United Kingdom, January 25th, 2021 Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced the latest addition to the Imperas RISC-V Verification IP (VIP) solutions with the Floating-Point architectural validation test suites covering the RISC-V Specifications for 32bit Single-Precision (32F), 64bit Single-Precision (64F), and 64bit Double-Precision (64D). These tests extend the current Imperas range of tests for ratified and near-ratified specifications tests, and complement the de facto industry adoption of the Imperas RISC-V verification reference model.
Imperas releases new RISC-V Processor Verification IP to drive RISC-V adoption forward with a flexible methodology for all SoC adopters eejournal.com - get the latest breaking news, showbiz & celebrity photos, sport news & rumours, viral videos and top stories from eejournal.com Daily Mail and Mail on Sunday newspapers.