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Andes certifies Imperas RISC-V Reference Models for SIMD/DSP extension Imperas Software has announced that Andes Technology, a supplier of 32/64-bit RISC-V CPU cores and a member of the RISC-V International Association, has certified the Imperas reference models for the complete range of Andes IP cores with the new RISC-V P extension. As a consequence, developers will now be able to use the Imperas reference models to evaluate multicore design configuration options for SoC architecture exploration. The open standard RISC-V ISA (Instruction Set Architecture) has a modular structure based on multiple independent extensions that offer dedicated and enhanced functionality to optimize a processor for the target application. The SIMD/DSP extension, designated as ‘P’ in the specification description, supports efficient data processing applications and real-time requirements.

Charlie suRiscv internationalp extension task groupRiscv international associationImperas softwareAndes technologyInstruction set architectureசார்லி சுஅண்டெஸ் தொழில்நுட்பம்அறிவுறுத்தல் அமை கட்டிடக்கலை