Low-power HMAC SHA AES Accelerator The HMAC SHA AES Accelerator is a low-power low-gate count crypto core with DMA capability and local key storage. Compared to a software only solution, the core provides higher performances and additional security to applications.
By using dedicated hardware accelerators, the HMAC SHA AES Accelerator provides a first performance boost compared to software execution on the host processor. The second advantage is the ability to store keys in an integrated RAM via DMA, and keep these inaccessible, but usable, for the host/application.
The HMAC SHA AES Accelerator provides hardware cryptographic algorithm implementations for optimal performance, user experience, battery lifetime and robust security.
CC-100IP-RF Analog and RF Sensitivity Enhancement IP The CC-100IP-RF is a RF and Analog Frontend Sensitivity Enhancement IP Block that embeds a Hyper-Capacitor with a Capacitance Multiplication, Series Inductance Nullification, Cybersecurity Enhancement and Energy Harvesting capabilities. The IP accomplishes Signal Sensitivity Enhancment by improving the PSRR of sensitive RF and Analog front end receivers. CC-100IP-RF Hyper-Bypass Capacitor creates an adjustable Impedance controlled point in IC power grids aiding in maximum on chip supply line filtering, Impedance matching for Power Grid flat frequency response, showing an up to a 600X improvement in effective and reservoir capacitance. The IP features a circuit noise activated dynamic input current controlled reservoir capacitance, and can function as a “stand-alone” on Chip DCAP, or work in parallel with existing DCAP structures. Due to the embedded IP negative feedback, the CC-100 features a 25% reduction in Hyper-Capa
PHY IP for PCIe 5.0 in TSMC N7 The multi-channel DesignWare® PHY IP for PCI Express® (PCIe®) 5.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for higher bandwidth. The PHY meets the needs of today’s high-speed chipto-chip, board-to-board, and backplane interfaces while being extremely low in power and area.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.
The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipmen
TSS GDDR6 PHY on TSMC 12nm from Openedges The GDDR6 OPHY utilizes state-of-the-art architecture in full custom analog mixed-signal design to overcome the problem of long-term impedance drift and clock phase drift, allowing impedance and clock phase updates without the need to interrupt data traffic. The programmable timing PHY boundary combines flexibility with analog precision, and the result is ultra low PHY read/write latency between OMC and the GDDR6 DRAM without sacrificing performance.
At the system level, the GDDR6 OPHY was designed with minimal package substrate layer and PCB layer count in mind. This enables the integration of a GDDR6 memory sub-system solution in cost sensitive applications, such as consumer edge devices, AI, GPU, HPC, STB, SSD controllers, and application processors.
All-in-one IP including body-bias voltage regulator, low power sensors and control loop Foundation IP independent View see the entire get in contact with
Adaptive Body-Bias Subsystem enabling Process, Voltage & Temperature compensation to leverage FDSOI body-biasing capabilities Supplier
Block Diagram of the Adaptive Body-Bias Subsystem enabling Process, Voltage & Temperature compensation to leverage FDSOI body-biasing capabilities FDSOI IP