RT-660 DPA-Resistant Programmable Root-of-Trust Security Processor for Govt/Aero/Defense FIPS-140 Rambus Hardware Root of Trust RT-660 is a fully-programmable hardware security core offering security by design. It protects against a wide range of attacks through state-of-the-art anti-tamper and security techniques.
Government hardware most often requires higher security protections due to sensitive information being stored or processed. As with every product within the CryptoManager Root of Trust 600-series, the RT660 features our 32-bit RSIC-V siloed and layered secure co-processor, along with dedicated secure memories.
The RT-660 adds an additional layer of protection thru the implementation of Differential Power Analysis (DPA)-protected cryptographic accelerators, including AES-AE-16, HMAC 512, 3DES, RSA 4K, ECC 521, RBG, and a NIST-compliant Random Bit Generator. Satisfying a requirement of most government applications, the RT-660 core is FIPS-140-2 compliant. The id
Body bias voltage generator - GLOBALFOUNDRIES 22FDX The Racyics® ABX Generator IP is a body bias voltage generator for the Racyics® ABX Platform for GLOBALFOUNDRIES 22FDX® technology. It contains a closed loop body bias regulation loop to generate N-well and P-well bias voltages for adaptive compensation of process, voltage and temperature (PVT) variations during device operation. View see the entire get in contact with Body bias voltage IP
Ultra-Fast Baseline and Extended JPEG Decoder Core This JPEG decompression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extremely high pixel rates.
The JPEG-DX-F Decoder decompresses JPEG images and the video payload for Motion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats.
Depending on its configuration, the decoder processes from two to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-EX-F Encoder Core. This Encoder-Decoder pair provide an extremely cost effective solution for streaming or archiving UHD (4K/8K) video, or very high frame rates at lower resolutions.
DPA Resistant Cryptographic Accelerator Core ChaCha20 – Fast Rambus DPA Resistant Hardware Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA. ChaCha 20 Fast DPA resistant cryptographic accelerator core.
The DPA Resistant Hardware cores offer chipmakers an easy-to-integrate technology-independent soft-macro security solution with built-in side-channel resistance for cryptographic functions across a wide array of devices.
These high-performance cores provide a higher level of protection than standard security cores, while improving time-to-market, as all the cores are validated DPA countermeasures. It is highly flexible for integration with standard cipher modes such as Cipher Block Chaining (CBC), Counter (CTR) and Authenticated Encryption mode / Galois Counter (GCM) modes. The fast AES core performs AES encryption with DPA protection using only 2 clock cycles per AES round, outperforming any existin
AES Key Wrap Accelerator The EIP-37 is the IP for accelerating the AES Key Wrap cipher algorithm (NIST-Key-Wrap & RFC3394). Designed for fast integration, low gate count and full transforms, the EP-37 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into SoCs that need high speed key wrap and (key) storage or key import and export systems View see the entire get in contact with AES IP