Highlights: • New solution accelerates IP-to-SoC-level verification for complex memory controllers, PHYs and devices for LPDDR5x, DDR5, HBM3 and GDDR6 protocols • Up to 10X increase in verification throughput enables total IP-to-SoC-level verification of advanced designs with multiple DDR interfaces SAN JOSE, Calif., January 20, 2022 Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced a…