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High Performance DDR4/3 Memory Controller IP Core

High Performance DDR4/3 Memory Controller Mobiveil s DDR4/3 Memory Controller is a highly flexible and configurable design targeted for high performance enterprise server and real-time consumer applications that utilize computational elements like graphics controllers, general purpose, digital signal processors, etc. The controller architecture is carefully tailored to achieve reliable high-frequency operation, dynamic power management, error injection and support for rapid system debug. DDR4/3 Controller is part of Mobiveil’s Storage and Memory controller family of IP solutions which also includes LPDDR2/3, UNEX, IFC, and eSDHC IP cores. The controller s simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible AXI System interface ma

DVB-S2X WideBand Demodulator IP IP Core

DVB-S2X WideBand Demodulator IP This is a high-performance, dual high-symbol-rate (HSR) DVB-S2/S2X demodulator IP extarcted from production chipsets with integrated tuner and silcon proven technology. The demodulators are compliant with Annex M of the DVB-S2 specification EN 302 307 and can demodulate signals up to 500 Msymbol/s. Each HSR demodulator may demodulate up to 2 slices. This implements 8 multi-standard demodulators capable of DVB-S, DTV legacy, DVB-S2 and DVB-S2X broadcast-profile signal processing. This IP incorporates a high-speed DVB-S2 forward error corrector (FEC) which is designed to handle up to 720 Mchannel-b/s at its input. This allows for 8 simultaneous 8PSK decodes at 30 Msymbol/s. This capacity is shared between the demodulators and may be allocated at will, provided that the maximum capacity limit is not exceeded.This IP features four integrated full-band capture tuners which cover the band 950 to 2150 MHz. The signal is sampled by high-performance an

RT-660 DPA-Resistant Programmable Root-of-Trust Security Processor for Govt/Aero/Defense FIPS-140

RT-660 DPA-Resistant Programmable Root-of-Trust Security Processor for Govt/Aero/Defense FIPS-140 Rambus Hardware Root of Trust RT-660 is a fully-programmable hardware security core offering security by design. It protects against a wide range of attacks through state-of-the-art anti-tamper and security techniques. Government hardware most often requires higher security protections due to sensitive information being stored or processed. As with every product within the CryptoManager Root of Trust 600-series, the RT660 features our 32-bit RSIC-V siloed and layered secure co-processor, along with dedicated secure memories. The RT-660 adds an additional layer of protection thru the implementation of Differential Power Analysis (DPA)-protected cryptographic accelerators, including AES-AE-16, HMAC 512, 3DES, RSA 4K, ECC 521, RBG, and a NIST-compliant Random Bit Generator. Satisfying a requirement of most government applications, the RT-660 core is FIPS-140-2 compliant. The id

Body bias voltage generator - GLOBALFOUNDRIES 22FDX

Body bias voltage generator - GLOBALFOUNDRIES 22FDX The Racyics® ABX Generator IP is a body bias voltage generator for the Racyics® ABX Platform for GLOBALFOUNDRIES 22FDX® technology. It contains a closed loop body bias regulation loop to generate N-well and P-well bias voltages for adaptive compensation of process, voltage and temperature (PVT) variations during device operation. View see the entire get in contact with Body bias voltage IP

Ultra-Fast Baseline and Extended JPEG Decoder Core

Ultra-Fast Baseline and Extended JPEG Decoder Core This JPEG decompression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extremely high pixel rates. The JPEG-DX-F Decoder decompresses JPEG images and the video payload for Motion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. Depending on its configuration, the decoder processes from two to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-EX-F Encoder Core. This Encoder-Decoder pair provide an extremely cost effective solution for streaming or archiving UHD (4K/8K) video, or very high frame rates at lower resolutions.

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