Verifying Dynamic Clock switching in Power-Critical SoCs
By Sarita Yadav, eInfochips - An arrow company
As technology advance, we see complex SoCs emerging in the market with multiple interfaces. These complex SoCs can have multiple clocks driving multiple modules, which may be getting divided further to generate new clocks in the chip and so the complexity increases.
Dynamic clock switching means that the clock frequency changes anytime during simulation, even in the middle of ongoing transactions. Most of the time, to verify a device under test (DUT), we prepare a testplan and all features are verified by generating stimulus, developing test cases, and comparing with scoreboard, checkers, predictor models, assertions, and coverage. Along with other features, one of the very important factors to consider during verification is the clocks. We perform register testing to ensure all registers in DUT gets updated as expected, which covers clock registers as well. But the clock regist