Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, has announced the latest release of the Riviera-PRO, providing support for system simulation of Versal Adaptive Compute Acceleration Platform (ACAP) designs.
Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs
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Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs
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Automated static linting and CDC analysis for FPGA and SoC FPGA designs
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Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has announced that it has updated its linting tool ALINT-PRO to enhance the support of Microchip Technology’s Libero SoC Design Suite.