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SoC design teams are tasked with completing full system-level verification before the creation of expensive production masks. To accomplish this task requires the teams to thoroughly vet all hardware blocks, all interactions between those blocks, and the purpose-built software created for the end application before the chip is even built. While hardware emulators and desktop FPGA prototype boards are two well-known participants in this verification, enterprise FPGA prototype platforms are now taking their place alongside them as the third participant. While simulation dominates in the early stages of a design, its use is limited to circuit blocks due to inadequate performance. Once full-chip verification begins, greater speed is needed both to handle the enormous number of tests required to achieve full hardware coverage and to integrate the software with hardware. Emulation has taken on the bulk of this burden. In parallel, when RTL code reaches stability, validation of software ap

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