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Cadence Digital Full Flow Achieves Certification for GlobalFoundries® 12LP/12LP+ Process Platforms

Highlights: • Certification enables customers to advance the design of aerospace, hyperscale computing, AI, mobile and consumer applications using Cadence and GF® technologies • Cadence digital full flow optimized for the GF 12LP/LP+ process platforms enables mutual customers to reach PPA goals faster and deliver new products to market with shorter design cycles SAN JOSE,…

Cadence Digital Full Flow Achieves Certification for GlobalFoundries 12LP/12LP+ Process Platforms

Cadence Digital Full Flow Achieves Certification for GlobalFoundries 12LP/12LP+ Process Platforms
hpcwire.com - get the latest breaking news, showbiz & celebrity photos, sport news & rumours, viral videos and top stories from hpcwire.com Daily Mail and Mail on Sunday newspapers.

Cadence Cerebrus to Enable Chip Design with ML: PPA Optimization in Hours, not Months

Cadence Cerebrus to Enable Chip Design with ML: PPA Optimization in Hours, not Months
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Cadence and UMC collaborate on 22ULP/ULL reference flow certification

Cadence and UMC collaborate on 22ULP/ULL reference flow certification Cadence Design Systems and the semiconductor foundry, UMC, have announced that the Cadence digital full flow has been optimised and certified for the UMC 22ULP/ULL process technologies to accelerate consumer, 5G and automotive application design. The flow, which incorporates leading implementation and signoff technology for ultra-low power designs, will enable customers to achieve a much faster path to tape-out. The Cadence digital full flow that has been optimized for use on UMC’s 22ULP/ULL process technologies includes the Innovus Implementation System, Genus Synthesis Solution, Liberate Characterization, Quantus Extraction Solution, Tempus Timing Signoff Solution, Litho Physical Analyzer and Physical Verification System.

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