January 28, 2021
Synopsys Demonstrates Silicon Proof of DesignWare 112G Ethernet PHY IP in 5nm Process for High-Performance Computing SoCs
DesignWare IP With Unmatched Long-Reach Performance Results Supports Insertion Loss Greater Than 40dB and Delivers Power-Efficiency of Less Than five pJ/Bit
MOUNTAIN VIEW, Calif., Jan. 28, 2021 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS) today announced the silicon proof of DesignWare
® 112G Ethernet PHY IP in 5nm FinFET process, delivering significant performance, power and area advantages. The area-efficient DesignWare 112G Ethernet PHY enables designers to optimize highly dense system-on-chips (SoCs) with placement-aware IP that maximizes bandwidth per die-edge through stacking and placement on all four edges of the die. To extend performance, the DesignWare 112G PHY demonstrates zero bit-error rate post forward-error correction in greater than 40dB channels while offering power-efficiency of less than five picojoules per bit (pJ/bit).