The FPGA Lock is a small FPGA IP core that uses the $0.52 Microchip ATSHA204A hardened crypto authentication IC and one FPGA pin to lock down FPGAs and .
The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package .
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offering .
Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in standard CMOS and BCD process .