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The main objective of this article is to explain synthesis flow and post-synthesis netlist quality checks. In ASIC flow, synthesis is the part of the front-end design, while the back-end design takes the synthesized netlist as an input. So, the synthesized netlist should meet all netlist quality checks to reduce multiple iterations, which reduces the turnaround time and efforts.

Vallabh vidyanagarAshish trapasiyaDhanyakumar shahSynopsys designFusion compilerFor physicalAware synthesisWire load modelPhysical awareConnect supply netLogic equivalence checksSenior physical design engineer