The agileSensorIF Subsystem is an efficient and highly integrated sensor interface for SoCs/ASICs. Featuring multiple Analog-to-Digital converters (agileADC), .
Based in Cambridge Agile Analog, which was established in 2017, looks to provide designers of ASICs and SoCs with the analogue IP that they ‘really want and need’.
The agilePMU Subsystem is an efficient and highly integrated power management unit for SoCs/ASICs. Featuring a power-on-reset, multiple low drop-out regulators, .
The monitoring of process, voltage and temperature variations are critical to optimise power and performance for modern SoCs/ASICs, especially for advanced .
The agileSMU Subsystem is a low power integrated macro consisting of the essential IP blocks required to securely manage waking up a SoC from sleep mode. .