Integrating dimensions to get more out of Moo

<p>In a study published today (Jan. 10) in the journal&nbsp;<a href="https://www.nature.com/articles/s41586-023-06860-5">Nature</a>, Saptarshi Das, an associate professor of engineering science and mechanics and co-corresponding author of the study, and his team suggest a way to fit more transistors on a chip by seamlessly implementing 3D integration with 2D materials.</p>

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