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Posted July 19th, 2021 for Imperas Imperas simulation technology and reference model available for free, including test suites for basic processor hardware verification and compliance testing. Oxford, UK – July 19th, 2021  – Imperas Software Ltd ., the leader in RISC-V processor verification technology, announces the latest updates to riscvOVPsimPlus with support for the near ratified P extension and architectural validation test suites. The P (or Packed SIMD/DSP) extension is a significant addition to the flexibility of the modular RISC-V ISA (Instruction Set Architecture); it supports real-time data processing applications as part of the main processor pipeline without the need for the associated inefficiencies of a co-processor. For processor hardware verification, a basic test suite helps ensure implementations have a basic software level compatibility to the new P extension as a reference to the developers’ interpretation of the written specification.

United kingdomSimon davidmannChuanhua changWei wuRiscv internationalp extension task groupImperas software ltdAndes technology corporationImperas softwareInstruction set architectureInstruction set simulatorArchitectural validation test suitesOpen virtual platformsCadence palladiumImperas software limitedஒன்றுபட்டது கிஂக்டம்வெய் வு