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Cadence Announces New Low-Power IP for PCI Express 5.0 Specification on TSMC N5 Process Cadence Design Systems, Inc. announced immediate availability of Cadence® IP supporting the PCI Express® (PCIe®) 5.0 specification on TSMC N5 process technology. The next follow-on version on TSMC N3 process technology is expected to be taped out in early 2022. Collaboration with major customers is ongoing for N5 SoC designs targeting hyperscale computing and networking applications. The Cadence IP for PCIe 5.0 technology consists of a PHY, companion controller and Verification IP (VIP) targeted at SoC designs for very high-bandwidth hyperscale computing, networking and storage applications. With Cadence’s PHY and Controller Subsystem for PCIe 5.0 architecture, customers can design extremely power-efficient SoCs with accelerated time to market.

Al yanesSuk leeSanjive agarwalaTom fawcettLab production business unitDesign infrastructure management divisionCadence design systems incIp group at cadenceDesign systemsController subsystemCompute express linkProduction business unitIntelligent system designசூக் லீடோம் ஃபாஸிட்வடிவமைப்பு உள்கட்டமைப்பு மேலாண்மை பிரிவு